1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems. In particular, the present invention relates to a method and system that improve the model build and simulation processes in order to allow a designer to easily instrument and monitor a simulation model. More particularly, the present invention relates to overriding signals within hardware description language models during simulation.
2. Description of the Related Art
Verifying the logical correctness of a digital design and debugging the design, if necessary, are very important steps in most digital design processes. Logic networks are tested either by actually building networks or by simulating networks on a computer. As logic networks become highly complex, it becomes necessary to simulate a design before the design is actually built. This is especially true when the design is implemented as an integrated circuit, since the fabrication of integrated circuits requires considerable time and correction of mistakes is quite costly. The goal of digital design simulation is the verification of the logical correctness of the design.
In a typical automated design process that is supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level description utilizing a hardware description language (HDL), such as VHDL, producing a representation of the various circuit blocks and their interconnections. The ECAD system compiles the design description into a format that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the design prior to developing a circuit layout.
A simulator is typically a software tool that operates on a digital representation, or simulation model of a circuit, and a list of input stimuli representing inputs of the digital system. A simulator generates a numerical representation of the response of the circuit which may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general purpose computer or on another piece of electronic apparatus specially designed for simulation. Simulators that run entirely in software on a general purpose computer will hereinafter be referred to as “software simulators”. Simulators that are run with the assistance of specially designed electronic apparatus will hereinafter be referred to as “hardware simulators”.
Usually, software simulators perform a very large number of calculations and operate slowly from the user's point of view. In order to optimize performance, the format of the simulation model is designed for very efficient use by the simulator. Hardware simulators, by nature, require that the simulation model comprising the circuit description be communicated in a specially designed format. In either case, a translation from an HDL description to a simulation format, hereinafter referred to as a simulation executable model, is required.
Simulation has become a very costly and time-consuming segment of the overall design process as designs become increasingly complex. Therefore, great expense is invested to ensure the highest possible accuracy and efficiency in the processes utilized to verify digital designs. A useful method of addressing design complexity is to simulate digital designs at several levels of abstraction. At the functional level, system operation is described in terms of a sequence of transactions between registers, adders, memories and other functional units. Simulation at the functional level is utilized to verify the high-level design of high-level systems.
At the logical level, a digital system is described in terms of logic elements such as logic gates and flip-flops. Simulation at the logic level is utilized to verify the correctness of the logic design. At the circuit level, each logic gate is described in terms of its circuit components such as transistors, impedences, capacitances, and other such devices. Simulation at the circuit level provides detailed information about voltage levels and switching speeds.
VHDL is a higher level language for describing the hardware design of complex devices. The overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are often individually designed by different design engineers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design. Another advantage of this approach is that errors in a design entity are easier to detect when that entity is simulated in isolation.
Comprehensive model verification often requires modeled signal values to be dynamically overridden during a simulation run. For example, a bus within an integrated circuit may carry signals that provide error correction values. Such error correction signals, in conjunction with bus data transmission signals, can be utilized to determine when inadvertent bus signal alterations occur due to external physical causes. An example of such an external physical cause is electrical noise near a bus signal that alters the bus signal value. Error correction signals generated at the source of the bus are examined by error correction logic at the bus destination that then corrects the error.
The simulation process includes no direct analogue to the external physical circumstances that can alter the bus signals. During simulation, error correction and bus signals are faithfully represented without inadvertent alteration.
Simulations of a given model on a simulator are typically controlled by a program, hereinafter referred to as the RTX (Run Time executive), written in a high level language such as C or C++. A simulator provides interface routines that an RTX calls to control simulation. These routines implement functions for reading signal values out of a model, cycling a model, altering signals values within a model, etc.
In order to effectively simulate and verify error correction logic, a simulation run must be altered to include instructions for overriding bus signals. Typically, an RTX calls a simulator interface routine, herein after referred to as PUTFAC, to directly alter a signal value during simulation thus injecting an error and precipitating activation of the error correction logic.
Using the RTX and PUTFAC to dynamically alter signals during simulation has two inherent shortcomings. First, the PUTFAC routine performs poorly on hardware simulators. Second, RTX is typically written in a high level programming language that may be unfamiliar to design engineers conversant in HDLs such as VHDL or Verilog.
It would therefore be useful to provide a means for altering signal values within a simulation model that is more accessible to design engineers, and furthermore, performs efficiently when utilized in conjunction with a hardware simulator.